- Fixup for the PPC Power6/DFP instructions disassembly (BZ 230000).
- New testcase for the GCORE buffer overflow (for BZ 238285, formerly
235753).
- Related: rhbz#230000 rhbz#238285 rhbz#235753
This commit is contained in:
Jan Kratochvil
parent
1499556e03
commit
acb618c727
3 changed files with 345 additions and 4 deletions
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@ -552,3 +552,189 @@ https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=232353
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/* The objfile containing the symbol whose location we're computing. */
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/* Used (only???) by thread local variables. The objfile in which
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https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=230000
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Fixes embarrassing errors in the ppc dfp instructions committed some
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time ago. IBM numbers bits in architecture manuals starting from zero
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in the most signifigant bit. Fields are marked by numbering their
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most signifigant bit too. This means some translating is required when
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filling out new powerpc_operand entries. You can't just plug IBM
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numbers into the shift counts. Also, Z_MASK is too big for
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instructions that take RMC operands.
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* ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift.
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(Z2_MASK): Define.
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(powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
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--- ./opcodes/ppc-opc.c 19 Apr 2007 01:39:31 -0000 1.91
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+++ ./opcodes/ppc-opc.c 20 Apr 2007 09:52:09 -0000
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@@ -530,8 +530,9 @@ const struct powerpc_operand powerpc_ope
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#define SIMM VD + 1
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{ 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
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- /* The UIMM field in a VX form instruction. */
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+ /* The UIMM field in a VX form instruction, and TE in Z form. */
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#define UIMM SIMM + 1
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+#define TE UIMM
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{ 5, 16, NULL, NULL, 0 },
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/* The SHB field in a VA form instruction. */
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@@ -564,31 +565,23 @@ const struct powerpc_operand powerpc_ope
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#define A_L MTMSRD_L
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{ 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
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- /* The DCM field in a Z form instruction. */
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-#define DCM MTMSRD_L + 1
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- { 6, 16, NULL, NULL, 0 },
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-
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- /* Likewise, the DGM field in a Z form instruction. */
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-#define DGM DCM + 1
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- { 6, 16, NULL, NULL, 0 },
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-
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-#define TE DGM + 1
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- { 5, 11, NULL, NULL, 0 },
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-
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-#define RMC TE + 1
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- { 2, 21, NULL, NULL, 0 },
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+#define RMC A_L + 1
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+ { 2, 9, NULL, NULL, 0 },
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#define R RMC + 1
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- { 1, 15, NULL, NULL, 0 },
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+ { 1, 16, NULL, NULL, 0 },
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#define SP R + 1
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- { 2, 11, NULL, NULL, 0 },
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+ { 2, 19, NULL, NULL, 0 },
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#define S SP + 1
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- { 1, 11, NULL, NULL, 0 },
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+ { 1, 20, NULL, NULL, 0 },
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/* SH field starting at bit position 16. */
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#define SH16 S + 1
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+ /* The DCM and DGM fields in a Z form instruction. */
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+#define DCM SH16
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+#define DGM DCM
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{ 6, 10, NULL, NULL, 0 },
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/* The L field in an X form with the RT field fixed instruction. */
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@@ -1683,6 +1676,7 @@ extract_tbr (unsigned long insn,
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/* The mask for a Z form instruction. */
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#define Z_MASK ZRC (0x3f, 0x1ff, 1)
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+#define Z2_MASK ZRC (0x3f, 0xff, 1)
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/* An X_MASK with the RA field fixed. */
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#define XRA_MASK (X_MASK | RA_MASK)
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@@ -4639,8 +4633,8 @@ const struct powerpc_opcode powerpc_opco
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{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
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{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
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-{ "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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-{ "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
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{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
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@@ -4678,20 +4672,20 @@ const struct powerpc_opcode powerpc_opco
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{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
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{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
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-{ "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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-{ "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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-{ "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
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-{ "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
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+{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
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+{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
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{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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-{ "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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-{ "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
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@@ -4699,8 +4693,8 @@ const struct powerpc_opcode powerpc_opco
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{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
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{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
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-{ "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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-{ "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
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{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
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@@ -4766,8 +4760,8 @@ const struct powerpc_opcode powerpc_opco
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{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
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{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
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-{ "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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-{ "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
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{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
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@@ -4842,8 +4836,8 @@ const struct powerpc_opcode powerpc_opco
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{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
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{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
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-{ "drrndq", ZRC(63,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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-{ "drrndq.", ZRC(63,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
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{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
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@@ -4856,8 +4850,8 @@ const struct powerpc_opcode powerpc_opco
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{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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-{ "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
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-{ "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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+{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
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+{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
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{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
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{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
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@@ -4868,8 +4862,8 @@ const struct powerpc_opcode powerpc_opco
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{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
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-{ "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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-{ "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
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@@ -4883,8 +4877,8 @@ const struct powerpc_opcode powerpc_opco
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{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
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{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
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-{ "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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-{ "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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+{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
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{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
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{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
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--
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Alan Modra
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IBM OzLabs - Linux Technology Centre
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